1. Field of the Invention
This invention relates to a relatively small size data processing system, and more particularly to a memory access control system in use with a relatively small size data processing system.
2. Description of the Related Fields
FIG. 1 shows a configuration of a relatively small size data processing system such as a personal computer. In the configuration of FIG. 1, memory 33 is connected to system bus 35. CPU 31 accesses to memory 33, via system bus 35. Such access system is called a system-bus memory access system.
There is another proposal of a memory access system in which CPU 41 accesses memory 42 through dedicated local bus 47, as shown in FIG. 2. This type of the access system can make a high speed access to memory 42, because there is no bothering of competitive acquisition of the bus line. The memory access system using the local bus is called a local-bus memory access system.
In the architecture of the data processing system configured as shown in FIG. 1, the memory access by CPU 31 and the memory access by direct memory access controller (DMAC) 32 are in the same level, with respect to system bus 35. Therefore, even if memory 33 per se is operable at a high speed, the control of system bus 35 limits increase of the access speed when high speed memory 33 is accessed.
In the data processing system configured as shown in FIG. 2, DMAC 43 is allowed to access only low speed memory 44 coupled with system bus 46. In other words, it cannot access high speed memory 42. DMAC 43 controls mainly the data transfer between low speed memory 44 and input/output (I/0) device 45. The access speed of DMAC 43 is limited by the operation speed of I/0 device 45. Therefore, even if DMAC 43 accesses low speed memory 44, it does not damage an operation speed of the system in any way. Since high speed memory 42 is directly accessed by CPU 41, the performance of high speed memory 43 per se, and that of CPU 41 as well can be fully utilized.
As the result of recent rapid development of semiconductor technology, the operation speed of CPU and memory has been increased. With increase of the operation speed, disadvantages of the architecture of the system-bus memory access system have been more distinguished. A possible measure for this is to employ the architecture of the local-bus memory access system. However, this measure will encounter the problem inherent in this architecture that DMAC 43 cannot directly access high speed memory 42. A software approach may solve this problem. Specifically, a memory address space of CPU 41 is divided into an address space accessible by DMAC 43 and an address space inaccessible by the same. The software does not access to high speed memory 42.
The software approach, however, involves a problem "There is a danger that a software based on the system-bus system architecture does not run in the local-bus system architecture". In other words, the software based on the system-bus system architecture is not compatible with that based on the local-bus system architecture.